Conventional transistor gate electrodes may employ a hard mask or etch stop layer, such as a silicon nitride layer, over a polysilicon gate layer to protect the gate layer during a subsequent etch, such as source/drain contact etch which might short the gate electrode if it is exposed. In the conventional subtractive process, the gate layer and then the etch stop layer are deposited in succession and etched together after a single lithographic operation to form a gate electrode stack.
As a departure from such subtractive gate electrode processes, replacement gate processes are becoming methods of choice for advanced transistor fabrication. A replacement gate process typically employs a dummy structure or mandrel around which other transistor features, such as dielectric spacers and doped substrate regions, are formed. Eventually, the mandrel is removed and replaced with a gate electrode material, such as a metal, having properties suitable for a high performance transistor.
However, replacement gate electrode processes, being additive, do not lend themselves well to incorporation of a stop layer over the gate layer. For example, the replacement gate layer may be deposited and planarized, but it is difficult to polish back a dielectric etch stop layer deposited as an overburden of the gate layer deposition. Such processes will generally leave some gate layer exposed. Alternatively, if a dielectric layer is deposited after a gate electrode material is planarized, that dielectric layer then needs to be patterned such that it provides an etch stop layer over the entire gate electrode surface while not extending a significant amount into other device regions, such as over a source or drain of the transistor. Any such patterning of the etch stop layer necessitates an additional lithography operation with associated alignment tolerances and costs.